A review on the compact modeling of parasitic capacitance: from basic to advanced FETs

Abstract

This paper presents a review on the development of parasitic-capacitance modeling for metal–oxide–semiconductor field-effect transistors (MOSFETs), covering models developed for the simple parallel-plate capacitance and the nonplanar and coplanar plate capacitances required for the intrinsic and extrinsic part of such devices. A comparative study of various extrinsic capacitance models with respect to a reference model is used to analyze the benefits of the various approaches. Capacitance models for basic MOSFETs and advance multigate FETs with two-dimensional (2D) and three-dimensional (3D) structures are reviewed. It is found that the elliptical field lines between the gate electrodes and source/drain region are modeled very well, while deviations of $$\pm 2 \%$$ in the orthogonal plate capacitance are observed when the gate electrode thickness is varied from 5 to 20 nm .