Abstract

Multi-core processor parallels two or more computing core in a single processor to enhance computational capability. Plenty of former researches are focused on CMP (Chip multi-processor), the most typical structure of multi-core processor. Thus deign of cache coherence, in particular, is one of the primary problems beyond other researches about CMP. In this paper, cache coherence protocol of CMP is fully presented, along with its advantages and disadvantages. Finally, some edging issues of cache coherence protocols are addressed in this paper.

Full Text
Paper version not known

Talk to us

Join us for a 30 min session where you can share your feedback and ask us any queries you have

Schedule a call

Disclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.