Abstract
The recent high-performance interfaces like DDR2, DDR3, USB and Serial ATA require their output drivers to provide a minimum variation of rise and fall times over Process, Voltage, and Temperature (PVT) and output load variations. As the interface speed grows up, the output drivers have been important component for high quality signal integrity, because the output voltage levels and slew rate are mainly determined by the output drivers. The output driver impedance compliance with the transmission line is a key factor in noise minimization due to the signal reflections. In this paper, the different implementations of PVT compensation circuits are analyzed for cmos45nm and cmos65nm technology processes. One of the considered PVT compensation circuits uses the analog compensation approach. This circuit was designed in cmos45nm technology. Other two PVT compensation circuits use the digital compensation method. These circuits were designed in cmos65nm technology. Their electrical characteristics are matched with the requirements for I/O drivers with respect to DDR2 and DDR3 standards. DDR2 I/O design was done by the Freescale wireless design team for mobile phones and later was re-used for other high speed interface designs. In conclusion, the advantages and disadvantages of considered PVT control circuits are analyzed.
Highlights
In any manufacturing step during the fabrication process of ICs, there are target specifications and there are manufacturing tolerances around each specification
The recent high-performance interfaces like DDR2, DDR3, USB and Serial ATA require their output drivers to provide a minimum variation of rise and fall times over Process, Voltage, and Temperature (PVT) and output load variations
As the interface speed grows up, the output drivers have been important component for high quality signal integrity, because the output voltage levels and slew rate are mainly determined by the output drivers
Summary
In any manufacturing step during the fabrication process of ICs, there are target specifications and there are manufacturing tolerances around each specification. The gate oxide thickness specification translates to slower devices (higher threshold voltage) for thicker oxides and faster devices for thinner oxides (lower threshold voltage) If such devices were used as a driver element, large variations in driver strengths and slew rates from the pre-driver should be expected. Mentations of PVT compensation circuits are analyzed for cmos nm and cmos nm technology processes These new PVT circuits are used for compensation of output resistance variation of high speed DDR I/O drivers implemented in sub-100 nm bulk and SOI technologies. The second PVT compensation circuit uses the digital compensation method This circuit was designed in the cmos65nm bulk technology and its electrical characteristics are matched with the requirements for I/O driver with respect to DDR3 standard. The advantages and disadvantages of considered PVT control circuits are analyzed
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