A review of nanoscaled bulk double gate and triple gate FETs for low standby power application

Abstract

The electrical characteristics of bulk double gate (DG) and triple gate (TG) FETs for low standby power application are reviewed using various peer reviewed literature. The study is focused on nanoscale devices up to channel length of 10nm. Junctionless (JL) and inversion mode (IM) structures together with other device improvement techniques have been explored from different research publications to optimize the device for low standby power application. The effect of device parameters e.g., channel length, fin dimensions, fin doping, gate dielectric and fin materials have been summarized using the findings reported till recent past. Further, the effects of variation in device parameters for the cases of inclusion and exclusion of Quantum Mechanical Effects are studied. Since the domain is wider than the reporting of a single literature, sometimes a few of the findings get scattered and appear to be uncorrelated in different literature. The implication of high k dielectric with quantum mechanical effects is one such important aspect. This work presents correlated study of such findings, and establishes their meaning with the overall functioning of the device. Altogether, the work establishes meaningful relation among various device characteristics of scaled bulk multi-gate devices reported in isolated literatures over the past decade.