A Resource Efficient Software-Hardware Co-Design of Lattice-Based Homomorphic Encryption Scheme on the FPGA

Abstract

Lattice-based homomorphic encryption schemes provide strong resistance against quantum and classical computer-based adversary security attacks. In this paper, we present a software-hardware co-design of two partially homomorphic encryption (PHE) schemes employing an ARM-SoC and an FPGA This provides necessary acceleration to PHE methods in the ecosystem mentioned above. The first PHE scheme is designed for generic homomorphic encryption, while the second scheme is aimed at resource optimized lightweight IoT-driven applications. For seamless assimilation, a robust and reliable low latency data transfer protocol is developed between the FPGA-based accelerator IP and ARM-SoC host system. The proposed PHE schemes are realized using Verilog HDL on multiple FPGA platforms. The proposed lightweight scheme is <inline-formula><tex-math notation="LaTeX">$52.71\times$</tex-math></inline-formula> more resource-efficient than the pipelined BGV RLWE-based method. It exhibits <inline-formula><tex-math notation="LaTeX">$1.43\times$</tex-math></inline-formula> and <inline-formula><tex-math notation="LaTeX">$1.29\times$</tex-math></inline-formula> better throughput than non-pipelined and pipelined realizations of the BGV RLWE-based scheme. The proposed hardware accelerators realized on FPGA platforms having lesser clock speed and consuming lower resources showcase significant speedup compared to their software implementations making our proposed method an efficient alternative to enhance security in edge-enabled IoT devices.