A Research and Design of Lightweight Convolutional Neural Networks Accelerator Based on Systolic Array Structure

Abstract

With the wide application of convolutional neural networks(CNNs) in the field of artificial intelligence, more attention has been paid to the architecture design of CNNs accelerator. But even so, there is little research on hardware acceleration of light-weight CNNs, and there is a lack of systematic and in-depth exploration of lightweight CNNs accelerator design space. In this paper, we propose a design scheme for the lightweight CNNs accelerator based on the systolic array structure. Taking the MobileNet series, the typical representative of lightweight CNNs, as the test benchmark, we carry out detailed experiments and research analysis on the accelerator performance under different data-flow modes and different core computing array scales. Based on the systematic and comprehensive experiments, we provide powerful experimental data supporting and scientific guidance for the design space of the systolic array based lightweight CNNs accelerator and the trade-off of various indicators including operational efficiency, acceleration ratio, cycle time and so on, which makes up for the blank of current research in this field, and makes great convenience for subsequent designers to develop lightweight CNNs accelerators. Through our research, MobileNet V1 is speeded up nearly 1.2 times under certain conditions.