A register-transfer-level fault simulator for permanent and transient faults in embedded processors

C Rousselle,H.T Vierhaus,T Mohaupt,M Pflanz,A Behling

doi:10.1109/date.2001.915148

A register-transfer-level fault simulator for permanent and transient faults in embedded processors

C Rousselle, H.T Vierhaus + Show 3 more

https://doi.org/10.1109/date.2001.915148

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Publication Date: Nov 13, 2002

Citations: 6

Affiliation: Kisters (Germany), Brandenburg University of Technology Cottbus-Senftenberg, Philips (Germany)

#Permanent Faults #Transient Faults + Show 4 more

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Abstract

HEARTLESS (Hierarchical Register-Transfer-Level Fault-Simulator for Permanent & Transient Faults) was developed to simulate the behavior of complex sequential designs like processor cores in case of transient and permanent faults. HEARTLESS can be enhanced by propagation over macros described in a C++ function. Available is a C-interface for access to internal signals during the simulation.

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