Abstract
Square root calculation is an important operation in digital signal processing. A parallel architecture design for predictive square root algorithm is introduced. It is a parallel version of our previous research of iterative square root algorithm architecture. This parallel design can produce square root and remainder values directly without any additional corrections and without any registers. It computes each coupled bits of input in homogenous treatments which consist of CAG (compare and generate) mechanism, addition, subtraction, and concatenation. Hence, the architecture design is low complexity and pipelinable. The 32-bit input architecture has been synthesized for FPGA Altera Cyclone II EP2C35F672C6. It only needs 580 logic elements and register-free.
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