Abstract
We propose a reflection self-canceling design technique for multidrop memory interfaces. In this technique, lengths of branch lines are designed, so that dominant multiple reflections become self-canceling. As a result, reflective intersymbol interferences (ISIs) can be greatly reduced to increase the bandwidth without utilizing serial resistor insertion, reflection compensation lines (RCLs), or advanced circuits, such as equalization circuits. Using the proposed and the conventional techniques, two eight-drop channels were designed with 50- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\Omega $ </tex-math></inline-formula> microstrip lines on FR-4 printed circuit board (PCB) and tested with the pseudo-random binary sequence (PRBS) 31 pattern for comparison. At 10.5 Gb/s, the worst eye height was measured 28.0 mV in the proposed design, while the worst eye diagram of the conventional design was closed. The proposed design achieved the maximum data rate of 12.5 Gb/s and achieved the worst eye height of 10.0 mV. The achieved data rate of 12.5 Gb/s is 95.3% faster than the prior art measured with an eight-drop channel without equalization circuits.
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