A Reduced Power MUX in 16Nm CMOS Technology

Abstract

A new 2:1 mux in 16nm cmos design, nmux, is presented in this paper. The proposed design uses dual assignment of threshold voltage and oxide width with a specific pattern. Static power, delay and PDP of nmux is compared with high performance application and low power application multiplexer. It is found that there is an improvement of 65.5% in static power and 63.4% in delay as compared to the multiplexer designed for low power applications. Static power in case nmux is reduced to 99.9% as compared to mux designed for high performance applications. The performance of nmux here is reduced to 5.3%. There is no loss in area in proposed mux.