A reconfigurable parallel FPGA accelerator for the kernel affine projection algorithm

Abstract

Kernel affine projection algorithm (KAPA) is an efficient online kernel learning method, because it not only inherits the advantages of other kernel adaptive filtering (KAF) algorithms, but also reduces the gradient noise significantly. More importantly, it provides a unifying framework for many KAF algorithms. However, suffering from huge computational load, especially when network size is large, it is not suitable for real-time applications. In order to extend its availability, we design a reconfigurable parallel FPGA accelerator for it. The generally used Gaussian kernel is chosen. Moreover, a novel quantization method is adopted to constrain the network size, so as to further reduce computational load and storage overhead. The proposed accelerator allows multiple input data to be processed simultaneously, accelerating the execution rate. Shift registers are used to record the results of different input data. The codebook and coefficients are updated for each input in sequential order along with the shifting of registers constantly. Finally, the FPGA accelerator with eight datapaths, which works at 100MHz, achieves an average speedup of 404.47 versus C code running on a 3GHz Intel(R) Core(TM) i5-2320 CPU.