A reconfigurable low power FPGA design with autonomous power gating and LEDR encoding

Abstract

Field Programmable Gate Arrays (FPGAs) are widely used to implement special purpose processors. FPGAs are economically cheaper for low quantity production because its function can be directly reprogrammed by end users. This paper investigates to design a reconfigurable low power Asynchronous FPGA cells. FPGAs consume high dynamic and standby power. In order to reduce the standby power by using autonomous fine grain power gating and reducing the dynamic power by using the level encoding dual rail (LEDR) architecture. The proposed autonomous fine-grain power gating method each lookup table has its own sleep transistor and related sleep controller. So when any lookup tables are inactive, they can be set to sleep mode immediately. LEDR encoding is used to data flow at input and output of FPGAs, it reduces the dynamic power. The circuit is simulated using Xilinx tool. Power reduction is achieved by selectively setting the functional units into a low leakage mode when they are inactive.