A Reconfigurable High Performance ASIP Engine for Image Signal Processing

Abstract

Emerging digital television applications and the conventional MPSoC architectures encounter drastically increasing performance and flexibility requirement. To display high quality of images on the display devices, several image processing has to be performed. However, these algorithms are nonstandard and change case by case. It is difficult to achieve real time processing by using general purpose processor or DSP. In this paper, we present a reconfigurable Application Specific Instruction-set Processor (ASIP) which can perform several image processing algorithms by using the same data path. It can complete several 1D filtering processing within 8 cycle/pixel, performing 16 times higher performance compare to conventional RISC processor. the performance of this ASIP can achieve the requirement of Full HD(1920×1080) application.