A reconfigurable Digital Signal Processor using residue number system

Abstract

Reconfigurable Computing has been evolving as a new platform for satisfying the simultaneous demand for application performance and flexibility placed over the present day DSP market. Since signal processing algorithms place significant demand on the processing power of the underlying platform, high performance reconfigurable architectures promise to be very efficient. The performance of traditional binary adders and multipliers for realizing Digital Signal Processing (DSP) algorithms are often limited by the carry propagation delay. As a result, non-binary number systems such as, the Residue Number System (RNS) is becoming popular in the field of DSP because of its efficient performance in addition and multiplication operations. This paper presents a novel reconfigurable architecture using RNS for implementing DSP algorithms. The proposed architecture has been validated on Field Programmable Gate Array (FPGA). A Finite Impulse Response (FIR) filter has been implemented on the proposed reconfigurable processor and the synthesis results are presented.