Abstract
Evolvable hardware is reconfigurable hardware plus an evolutionary algorithm. Continuous time recurrent neural networks (CTRNNs) have already been proposed for use as the reconfigurable hardware component. Until recently, however, nearly all CTRNN based EH was simulation based. This paper provides a design for a reconfigurable analog CTRNN computer that supports both extrinsic and intrinsic CTRNN evolvable hardware. The paper will fully characterize the design and demonstrate that configurations can be moved from simulation to hardware without difficulty. It will also discuss implications for an upcoming VLSI system that will combine the CTRNN circuitry with the learning engine on a single chip.
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