Abstract

This work demonstrates sub-ns time synchronization implemented in a real-time Fast Ethernet physical layer (PHY) chip. The chip is fabricated in a 180 nm technology of GLOBALFOUNDRIES. The PHY supports timestamping of ingress and egress frames with a resolution of 500 ps. Measurement results demonstrate the synchronization between two PHYs connected by up to 100 m long category 5 unshielded twisted pair cables. The time difference has a standard deviation of only 176 ps and a mean offset of 50.4 ps. Asymmetries in the cable are compensated by a simple calibration algorithm that is run at startup of the link within 1s.

Full Text
Paper version not known

Talk to us

Join us for a 30 min session where you can share your feedback and ask us any queries you have

Schedule a call