Abstract
We propose a combined physical/data link layer protocol for satellite communications that contains markers which allow for real-time Doppler synchronization on the satellite. Traditionally, the communication protocols on many cube- and nano satellites utilize data link layer protocols such as AX.25 or CC11XX, which also are widely used in ground based communication networks. Ground based protocols, such as AX.25 and CC11XX utilize a synchronization sequence at the beginning of the packet for the demodulator to achieve carrier and symbol synchronization. This is sufficient for stationary or slow moving transceivers. However for satellite communications, the Doppler frequency is time-varying and can be in the excess of 100's of kHz. Most conventional spacecraft radios can not reliably obtain frequency synchronization with these frequency offsets. To mitigate this, the transmission from the ground is typically Doppler pre-compensated based on apriori information of the satellite's trajectory. However in situations such as launch and early operations, for tactical users or for inter-satellite communications, this apriori information might be inaccurrate or unavailable. To mitigate this, we propose a combined physical/data link layer protocol, that spreads markers across the entire packet. These markers allow for online Doppler estimation and correction directly on the satellite. The proposed packet structure features a 48 bit sychronization marker at the beginning of the packet. This synchronization marker consists of five 8 bit markers, spaced such that the hamming distance to a nearest match is large. The phase rotation between these five markers can be used to perform a course Doppler correction. Additionally, there are 8 bit markers placed at regular intervals throughout the entire packet. These are utilized to perform a fine Doppler compensation. The proposed system is robust and can maintain synchronization when the Doppler is time-varying. The current implementation has 64 bits of data between each marker, and can be received on low power, limited capacity receivers in real time. The proposed protocol includes a double forward error correction (FEC) scheme. The inner $\text{FEC}$ is applied individually inside each 64 bit block and can correct two out of 15 symbols using a ( $\mathrm{n}=15, \mathrm{k}=11, \mathrm{m}=4$ ) Reed Solomon scheme. If the FEC on a block fails, the entire block can be marked as an erasure. The high level FEC, currently implemented as a ( $\mathrm{n}=255,\mathrm{k}=223,\mathrm{m}=8$ ) Reed Solomon coder, can correct up to 32 bytes marked as erasures or up to 16 bytes as errors per packet, where we currently transfer 1kb of data with a 80 bit header in a packet of 2280 raw bits (including synchronization and FEC). The proposed protocol is suitable for implementation in FPGAs and in software defined radio on personal computers. We currently have an early version of the protocol implemented on a FPGA that is running a raw data rate of 300 kbit/s on S-band. The protocol is currently in the process of being implemented on a cube satellite that will be launched in the near future.
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