A range of allowable number of input bits for tone free delta-sigma operation in digital MASH Delta-Sigma Fractional-N frequency synthesizers

Abstract

The fractional part of the division ratio in programmable Multi Modulus Divider (MMD) of Delta-Sigma (DS), Fractional-N (FN), Phase Locked Loop (PLL) frequency synthesizer, is generated and controlled by a Delta-Sigma Modulator (DSM). The digital DSM (DDSM) is a Finite State Machine (FSM) for a fixed DC input and due to its nonlinear chaotic behavior, undesirable spurs are observed in its high pass noise shaping output spectrum. Mitigation of these structured tones can be provided by different methods and one of these methods is called: maintaining controllable sequence length. In this approach, the idea is to allow the DDSM enough cycles to return to its initial starting state as an FSM. The operation time of the DDSM used in DS-FN-PLL frequency synthesizer cannot be chosen freely and is limited by the synthesizer lock time that is bounded and defined by the application standards. In this paper, a parameter called Modulator Tone Free Period (MTFP), the definition of the DDSM operation time required to guarantee a tone free spectrum, is presented. By using the parameter, MTFP, for Multi-stAge noise SHaping (MASH)-DDSM, the parameters of the DDSM and the DS-FN-PLL frequency synthesizer are related and the interval of the number of input bits for the DDSM, k, for 2nd, 3rd, 4th, and 5th order MASH structures are calculated and presented.