Abstract
A side-channel attack (SCA) on a reference-charge flow in successive approximation register (SAR) analog-to-digital converters (ADCs) discloses analog information acquired at a sensor frontend. A random interrupt dithering masks the correlation between analog input and reference charge flow by injecting extremely large dither of 1/4 full scale. An internal dither-tracking comparator yet guarantees rail-to-rail operation, resulting in no penalty in conversion accuracy. The comparator functions as a physical-random source for dithering. The unpredictable randomness based on comparator metastable operation by thermal noise enhances the security level while the shared use of the comparator reduces the associated hardware overhead. The additional silicon area penalty for the proposed technique is only 7% of an unprotected ADC core area. A 10-bit 1 MS/s secure SAR ADC was fabricated in 0.18- $\mu \text{m}$ CMOS. The measurement results demonstrate the proposed secure ADC suppresses the information leakage from 4.6 bit to 0.8 bit against reference-charge SCA.
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