Abstract
A simple new continuous-time CMOS comparator circuit with supply-to-supply input common-mode range is presented. This design uses parallel complementary decision paths to accommodate power-supply-valued inputs. The 2 decision results are combined at a current summing node, converted to a voltage, and buffered to drive voltage loads. The circuit requires an area of 416 /spl mu/m/spl times/221 /spl mu/m in a MOSIS 2-micron CMOS technology. It operates at 3 V and requires between 0.5 and 1.3 mA. Delays of between 54 and 282 ns have been measured.
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