Abstract
A hardware solution for the two 128-point o2DFT processors with a transform time of 125 μs needed in a 60-channel transmultiplexer for conversion between FDM and TDM signals is presented. It is shown how the mathematical redundancy of the processing can be removed, thus leading to a structure where the two transforms are realized as a 64-point FFT processor with 64 complex pre- and post-multiplications at the input and output, respectively. The processor is implemented as a radix-4 FFT algorithm which efficiently includes the necessary pre- and postmultiplications. A computer simulation is described in which the actual hardware arithmetic is exactly represented. The simulation verifies that the design objectives of the unit are satisfied with 16 bits in the processing. The resulting hardware, which uses only one MPY16HJ multiplier, is a special-purpose processor implemented in standard TTL technology with a power consumption of less than 20 W.
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