Abstract
This work presents a radiation resilient SRAM with a self-refresh scheme and error correction. The self-refresh scheme maintains the number of Single Event Upsets (SEUs) below a correctable value during the idle mode by checking and correcting stored data row by row. A 4KB SRAM test chip in 65nm CMOS technology demonstrates that the combination of the proposed self-refresh and the error correction improves the radiation tolerance significantly when the SRAM is under accelerated proton radiation. At 39.38 MeV of radiation energy and the operating frequency of 3.6MHz, the proposed schemes reduces the numbers of errors in the SRAM by 25× and 8× for the proton radiation durations of 10s and 50s, respectively.
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