A Quantum Pipeline for an Executable Quantum Instruction Set Architecture

Abstract

The existence of algorithm to machine gap has been accepted by the quantum computing domain experts, as the research community is struggling to realize the real power of quantum computing. The prime factor contributing to this gap is the large amount of quantum error correction (QEC) that is required during the execution of a quantum algorithm. For serial quantum computers, with just one processing zone, the coherence time of the qubits would have to grow with the increase in number of qubits, which is not realistic. To this end, the researchers have proposed a Software-Enabled Vertical Integration and Co-Design, which helps in developing optimized quantum compilers and produce easily verifiable solutions. The other option is to either increase the coherence time, decrease the time per quantum gate operation. However, both of these does not seem to be feasible, because both will lead to increase in execution time, albeit reducing the quantum error rate. Therefore, the feasible solution is to parallelize the quantum information processing (QIP), or the quantum instructions. In this paper, we design a simple quantum instruction set architecture (QISA) and a quantum pipelined architecture (QuPA). The proposed QISA is very similar to the classical instruction set architecture, except that the opcode is initially in an equal superposed state. Also the proposed QISA is grouped based on a certain common prefix, which helps to decode a particular (or group of) operation(s) with a higher probability. We demonstrate how the proposed QISA can be executed over the proposed QuPA with much less quantum cost compared to a general serial architecture. We show that the proposed QuPA has a gate cost of O(2^m) compared to the gate cost of the serial architecture, which is O(2^n), where m <=n.