A quantitative analysis of wiring lengths in 2D and 3D VLSI implementation of 2D systolic arrays

Abstract

Performance and cost of the widely used submicron 2D VLSI technology are primarily determined by interconnection delays and on-chip area. One of the possibilities for overcoming this problem is the use of the innovative 3D VLSI. In this structure, shortening of interconnection wires can be achieved, resulting in better performance and packing density. This analysis assumes an existing 3D channel routing methodology, based on the 2D channel routing methodology for standard-cell VLSI. The interconnection wire length in 3D and 2D structures is compared for several examples of systolic arrays. The experiments show that the average interconnection wire length in 3D structures is from 20% to 50% of the average interconnection wire length in 2D structures, depending on the number of active layers in 3D VLSI.