Abstract
This paper presents a low power and low noise quadrature RC oscillator based on a frequency locked loop. Voltage swing control of each of the two sub-oscillators reduces the effect of 1/f noise on the accumulated jitter. In addition, the use of quadrature phases greatly relieves timing constraints of sampling operations and helps the reduction of power consumption. With a discrete-time modeling of the quadrature oscillator, noise analysis is also provided for quantitative estimation of the circuit-driven effects on the phase noise. The proposed oscillator is fabricated using 180-nm CMOS process in an active area of 0.058mm2. The measurement shows a period jitter of 0.047% and a standard deviation of 0.94% in untrimmed frequency (444.9kHz) in a wafer. The oscillator achieves a figure-of-merit of 155 dBc/Hz at 100 Hz offset frequency.
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