Abstract
This article presents an accurate quadrature phase-locked loop (PLL) with quadrature phase mismatch calibration for 32 GS/s analog-to-digital converter (ADC). Due to the mismatches of clock distribution in layout and variations of the active devices, the quadrature phase of the sampling clock is significantly deteriorated. To solve the problem, a novel quadrature divider with phase calibration is induced in PLL loop. Moreover, a theoretical model of the quadrature divider is proposed to predict the performance and potential ability for phase calibration. Based on the theoretical and model analysis, the proposed PLL can realize accurate quadrature phase for high-speed real-time sampling system. The output frequency of PLL is 8 GHz with quadrature phases for 32 GS/s sampling rate. The proposed clock can realize 8-bit signal to noise ratio requirement with 16 GHz bandwidth. The proposed PLL was fabricated in 65-nm CMOS process with 28 mW dc power consumption under 1.2 V supply voltage. Testing results show that the phase noise of the clock is −127 dBc/Hz @10 MHz-offset frequency when the sampling speed is 27.4 GS/s. With proposed methods, the range of the phase error calibration is around ±20°.
Highlights
Nowadays, with the large amount of internet of thing (IoT) and wideband of 5G-communication technology, the bandwidth of the signals is getting wider and wider. To analyze these wideband signals with complex modulation types, the broadband analog to digital converters (ADCs) [1]-[3] are widely utilized to sampling the signals
The function of the track-and-hold amplifier (THA) is to sample the wideband analog signals and the sampled voltages are converted into digital codes by analog to digital converter (ADC)
ANALYSIS OF THE signal to noise ratio (SNR) PERFORMANCE RELATED TO CLOCK JITTER AND PHASE NOISE The spectrum purity of the phase-locked loop (PLL) is often described in terms of phase noise rather than time jitter [4]
Summary
With the large amount of internet of thing (IoT) and wideband of 5G-communication technology, the bandwidth of the signals is getting wider and wider. Paper [3] shows a 56 GS/s ADC with 256 parallel channels and speed of each channel is only several hundred MS/s With this time-interleaved structure, the high-speed sampling system design challenge moves to front-end THA design and clock distribution. Based the above system analysis, quadrature-rate samplers with hierarchy sampling structure can unify two superiorities and the design challenge of the sampling system is quadrature phase clock with low clock jitter, low clock skew and high stability over process, voltage and temperature (PVT) variation [6]-[10]. Resolution of conventional method is limited to picosecond
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