A PSRR Enhancing Method for GRO TDC Based Clock Generation Systems

Abstract

This paper discusses a supply noise sensitivity problem of the gated ring oscillator (GRO) based time-to-digital converter (TDC) in all-digital phase-locked loops (ADPLLs) and presents a power supply rejection ratio (PSRR) enhancing method. A replica supply noise monitoring circuit is designed to track supply noise and enable feed-forward error cancellation for high PSRR TDC design. A prototype ADPLL with the proposed self-monitored TDC is implemented in 65 nm CMOS to evaluate the supply noise sensitivity of the TDC in the frequency domain. Intermodulation spur generation problem due to noise coupling is also addressed and demonstrated in hardware. The experimental results show that the proposed method effectively suppresses supply noise induced spurs at the output of the ADPLL, achieving the PSRR of 27 dB and 38 dB with 1 MHz supply noise and 5 MHz intermodulation noise respectively.