Abstract
This paper describes a readout ASIC prototype designed by the CHIPIX65 project, part of RD53, for a pixel detector at HL-LHC . A 64×64 matrix of 50×50μm2 pixels is realised. A digital architecture has been developed, with particle efficiency above 99.5% at 3 GHz/cm2 pixel rate, trigger frequency of 1 MHz and 12.5μsec latency. Two analog front end designs, one synchronous and one asynchronous, are implemented. Charge is measured with 5-bit precision, analog dead-time below 1%. The chip integrates for the first time many of the components developed by the collaboration in the past, including the Digital-to-Analog converters, Bandgap reference, Serializer, sLVS drivers, and analog Front Ends. Irradiation tests on these components proved their reliability up to 600 Mrad.
Highlights
A prototype of pixel readout ASIC in 65 nm CMOS technology for extreme hit rate detectors at HL-LHC
: This paper describes a readout ASIC prototype designed by the CHIPIX65 project, part of RD53, for a pixel detector at HL-LHC
The chip integrates for the first time many of the components developed by the collaboration in the past, including the Digital-to-Analog converters, Bandgap reference, Serializer, sLVS drivers, and analog Front Ends
Summary
The active area contains the pixel matrix, which is structured as a digital sea, where the hit management logic lies, with so-called analog islands, containing the Analog Front Ends. These perform analog processing of the signal coming from the sensor, transforming it into a hit discrimination binary information to be passed to the digital circuitry. In the Chip Periphery, there is a dedicated readout stage for each Macro Column, called Macro Column Drainer These modules are connected to a shared logic, which handles the Pixel Regions configuration and buffers all the output information, feeding it to the serializer. (b) Close-up of the Pixel Matrix, where the two Front Ends can be distinguished
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