A proposed DDT/IDCT chip design using quaternary logic

K.W. Current

doi:10.1109/ismvl.1988.5146

A proposed DDT/IDCT chip design using quaternary logic

K.W. Current

https://doi.org/10.1109/ismvl.1988.5146

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Publication Date: Jan 1, 1988

Citations: 3

Affiliation: University of California, Davis

#Quaternary Logic #Quaternary Logic Circuits + Show 8 more

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Abstract

CMOS quaternary threshold logic circuits are used in the design of the instruction memory and arithmetic sections of a proposed single-chip implementation of a unified discrete cosine transform/inverse discrete cosine transform (DCT/IDCT) architecture. The chip is projected to be capable of real-time processing of 10-MHz video signals. The unified DCT/IDCT architecture is described, and the use of quaternary logic circuits is discussed. A 17.5% area savings has been achieved. >

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