A programming framework for data streaming on the Xeon Phi

S Chapeland,Alice Collaboration

doi:10.1088/1742-6596/898/7/072007

Abstract

ALICE (A Large Ion Collider Experiment) is the dedicated heavy-ion detector studying the physics of strongly interacting matter and the quark-gluon plasma at the CERN LHC (Large Hadron Collider). After the second long shut-down of the LHC, the ALICE detector will be upgraded to cope with an interaction rate of 50 kHz in Pb-Pb collisions, producing in the online computing system (O2) a sustained throughput of 3.4 TB/s. This data will be processed on the fly so that the stream to permanent storage does not exceed 90 GB/s peak, the raw data being discarded. In the context of assessing different computing platforms for the O2 system, we have developed a framework for the Intel Xeon Phi processors (MIC). It provides the components to build a processing pipeline streaming the data from the PC memory to a pool of permanent threads running on the MIC, and back to the host after processing. It is based on explicit offloading mechanisms (data transfer, asynchronous tasks) and basic building blocks (FIFOs, memory pools, C++11 threads). The user only needs to implement the processing method to be run on the MIC. We present in this paper the architecture, implementation, and performance of this system.

Highlights

ALICE and the O2 project ALICE [1] is the heavy-ion detector designed to cope with very high particle multiplicities to study the physics of strongly interacting matter at the CERN LHC
The Intel Xeon Phi platform At the time of the Technical Design Report (TDR) study, a new computing platform was just launched by Intel, targeting highperformance computing: the Intel Xeon Phi or MIC (Many Integrated Cores)
Not part of this study, we note that the example BZIP processing algorithm is not the most suitable task to run on Knights Corner (KNC) and Knights Landing (KNL) platforms

Summary

Introduction

The Intel Xeon Phi platform At the time of the TDR study, a new computing platform was just launched by Intel, targeting highperformance computing: the Intel Xeon Phi or MIC (Many Integrated Cores) It was released initially in 2013 with name Knights Corner (KNC) [5], followed by a newer version in 2016 named Knights Landing (KNL) [6]. The offload can be quite intrusive in the processing code to be tested, as it needs special control blocks to handle data movements and execution on the MIC This resulted in a prototype code mixing both control flow and algorithm. The key offload and workload distribution mechanisms of the first prototype have been extracted and optimized, in order to build a general purpose data streaming framework able to run code on MIC coprocessor boards, primarily for the benchmarking of different physics algorithm that will be needed in O2

The framework

Performance

Use case

Conclusions