Abstract
A multitude of privacy-enhancing technologies (PETs) has been presented recently to solve the privacy problems of contemporary services utilizing cloud computing. Many of them are based on additively homomorphic encryption (AHE) that allows the computation of additions on encrypted data. The main technical obstacles for adaptation of PETs in practical systems are related to performance overheads compared with current privacy-violating alternatives. In this article, we present a hardware/software (HW/SW) codesign for programmable systems-on-chip (SoCs) that is designed for accelerating applications based on the Paillier encryption. Our implementation is a microcode-based multicore architecture that is suitable for accelerating various PETs using AHE with large integer modular arithmetic. We instantiate the implementation in a Xilinx Zynq-7000 programmable SoC and provide performance evaluations in real hardware. We also investigate its efficiency in a high-end Xilinx UltraScale+ programmable SoC. We evaluate the implementation with two target use cases that have relevance in PETs: privacy-preserving computation of squared Euclidean distances over encrypted data and multi-input functional encryption (FE) for inner products. Both of them represent the first hardware acceleration results for such operations, and in particular, the latter one is among the very first published implementation results of FE on any platform.
Highlights
T HE ever-growing use of cloud computing has moved much of users’ sensitive data into service providers’ (e.g., Amazon, Facebook, Google, Microsoft, etc.) servers where the data is both stored and processed, and this trend is only expected to accelerate in the future thanks to the emerge of the Internet-of-Things (IoT)
We instantiate the proposed architecture as a Hardware/Software (HW/SW) codesign implemented in a Xilinx Zynq-7000 programmable SoC and provide performance evaluations with real hardware for two types of use cases: Firstly, we use the implementation for computing Squared Euclidean Distances (SEDs) over encrypted data, which has been used in multiple Privacy Enhancing Technologies (PETs) as discussed above
We presented an efficient HW/SW codesign on a programmable SoC for accelerating applications of Paillier encryption
Summary
T HE ever-growing use of cloud computing has moved much of users’ sensitive data into service providers’ (e.g., Amazon, Facebook, Google, Microsoft, etc.) servers where the data is both stored and processed, and this trend is only expected to accelerate in the future thanks to the emerge of the Internet-of-Things (IoT). We instantiate the proposed architecture as a Hardware/Software (HW/SW) codesign implemented in a Xilinx Zynq-7000 programmable SoC and provide performance evaluations with real hardware for two types of use cases: Firstly, we use the implementation for computing SEDs over encrypted data, which has been used in multiple PETs as discussed above This is the first published work that is capable of accelerating various types of PETs and shows that significant speed improvements can be achieved, increasing the practical adaptability of these PETs. Secondly, we use the design for accelerating an FE scheme for inner products from [31], [32] that is based on Paillier encryption. VI ends the paper by drawing conclusions and identifying certain directions for future work
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