Abstract

Pixel-parallel PE and SIMD architectures are widely used in high-speed image processing to enhance computing power. With fully exploiting the data level parallelism of low- and middle-level image processing, SIMD architecture is able to finish great amount of computation with much less instruction cycle thus satisfy the high-speed system requirement. The main computation parts in those SIMD image processing hardware is known as PE (processing element) and it is responsible for transferring, storing and processing the image data. This paper describes a high-speed vision system with superscalar PE to enhance system performance and its dedicated parallel computing language specifically devel-oped for this vision system. The vision system can achieve motion detection at more than 2000fps and face detection at more than 100 fps which overwhelms some general serial CPUs in the same applications.

Highlights

  • Researchers have been interested in high-speed vision system for decades [1]

  • Traditional machine vision systems which are composed of image sensor and general-purpose processor have heavy I/O load induced by large amount of image data transfer and lack of computational power for low- and middle-level processing

  • This paper describes a FPGA prototype of a programmable vision system implementing in Altera Cyclone III

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Summary

Introduction

Researchers have been interested in high-speed vision system for decades [1]. It can be applied in many fields, such as real-time object-tracking, machine vision, industry controls. Traditional machine vision systems which are composed of image sensor and general-purpose processor have heavy I/O load induced by large amount of image data transfer and lack of computational power for low- and middle-level processing. Using multi-level parallel processors to fully cover low-, middle-, and high-level image processing and with dedicated programming language this design can finish various high-speed image processing tasks. The image sensor exposure and data transfer of every frame consume large amount of time and instruction cycles greatly reduce the processing rate of our vision system.

System Architecture
PE Structure
Programming Language
FPGA Implementation
Findings
Conclusion
Full Text
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