Abstract
A simulation model that supports very accurate modeling of multiprocessors with a hierarchical, packet-switched interconnection network and private caches is explored. The simulation system contains workload simulators and a memory system simulator. The workload simulators are program-driven, i.e. they actually execute programs. The time unit of the simulator is the time between two consecutive memory references from the processors. The performance of the simulation model, although acceptable, could be improved using a trace-driven approach. The author shows that results obtained from trace-driven simulation methods in the course of multiprocessor performance evaluation are generally not valid. Furthermore, he shows that in the evaluation of certain processor architectural features, such as non-blocking architectures, the program-driven approach is necessary.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>
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