A Processor Power Management Scheme for Handheld Systems Considering Off-Chip Contributions

Abstract

Processor power management in handheld devices is the primary technique for exploiting power reduction while ensuring performance. Modern mobile devices require high performance at the system level to decode high-bitrate multimedia. For this reason, processor offloading using off-chip controllers is commonly exercised in this field. However, current power management techniques do not fully consider the offloading architecture. We propose a scheme to achieve power reduction through an empirical method, which detects and classifies off-chip usages, in addition to combining dynamic voltage scaling (DVS) with dynamic power management (DPM). We experimented with the proposed technique in a real hardware environment and achieved up to a 37% power reduction compared with previous schemes.