A Probabilistic Prediction Based Fixed-Width Booth Multiplier

Abstract

Fixed-width multipliers are widely used in multimedia and digital signal processing systems which are desirable to utilize a fixed operand length. In order to maintain the required computation accuracy, the truncation error has to be well compensated with minimum overhead. Recently, modified Booth algorithm has been increasingly employed in the fixed-width multiplier design so as to contribute further to the speedup and logic reduction. In this paper, a probabilistic prediction formula is proposed by taking the expected value of truncated partial products into account, which makes a zero mean error compensation. A simple compensation circuit is derived accordingly and plugged in to a fixed-width Booth multiplier design. Simulation results show that our proposed multiplier exhibits the best mean error and maximum absolute error when compared with existing designs. It achieves at least 20.82% energy reduction with 22.14% less silicon area with operand lengths of 8, 12, and 16 bits.