A Probabilistic Cache Sharing Mechanism for Chip Multiprocessors

Abstract

Capacity sharing is efficient for private L2 caches to utilize cache resources in chip multiprocessors. We propose a probabilistic sharing mechanism using reuse replacement strategy. This mechanism adopts decoupled tag and data arrays, and partitions the data arrays into private and shared regions. Probability is introduced to control the capability of each core to compete shared data resources. We assign high probabilities to cores with stress memory demands and dynamically adjust these probabilities corresponding to the monitored run-time memory demands. Simulation results of PARSEC benchmarks show that our mechanism exceeds conventional LRU managed private cache. Compared with reuse replacement managed private cache without sharing among cores, our mechanism achieves an average L2 miss rate reduction of 8.70%.