Abstract
Efficient full-chip thermal simulation is among the most challenging problems facing the EDA industry today, especially for modern 3D integrated circuits, due to the huge linear systems resulting from thermal modeling approaches that require unreasonably long computational times. While the formulation problem, by applying a thermal equivalent circuit, is prevalent and can be easily constructed, the corresponding 3D equations network has an undesirable time-consuming numerical simulation. Direct linear solvers are not capable of handling such huge problems, and iterative methods are the only feasible approach. In this paper, we propose a computationally-efficient iterative method with a parallel preconditioned technique that exploits the resources of massively-parallel architectures such as Graphic Processor Units (GPUs). Experimental results demonstrate that the proposed method achieves a speedup of 2.2× in CPU execution and a 26.93× speedup in GPU execution over the state-of-the-art iterative method.
Highlights
The evolution of the manufacturing technology of Integrated Circuits (ICs) has continued unabated over the past fifty years, according to the predictions of Moore’s law and has led to extremely complex circuits, and to analogous escalation of the problems related to the analysis and simulation of such circuits
The problem becomes more pronounced in modern technologies due to the multilayer 3D stacking, and the use of new device technologies, like FinFETsand Silicon on Insulator (SOI), which are more sensitive to the self-heating effect [2]
All experiments were executed on a Linux workstation, comprised of an Intel Core i7 processor running at 2.4 GHz and an NVIDIA Tesla C2075 Graphic Processor Units (GPUs) with 6 GB of main memory
Summary
The evolution of the manufacturing technology of Integrated Circuits (ICs) has continued unabated over the past fifty years, according to the predictions of Moore’s law and has led to extremely complex circuits (modern processors contain several billion transistors and are the most complex human construction), and to analogous escalation of the problems related to the analysis and simulation of such circuits. The continuous effort for smaller sizes, in the sub-45-nm era, and greater performance, as well as the new 3D structures have begun to outpace the ability of heat sinks to dissipate the on-chip power. The problem becomes more pronounced in modern technologies due to the multilayer 3D stacking, and the use of new device technologies, like FinFETsand Silicon on Insulator (SOI), which are more sensitive to the self-heating effect [2]. Stacking multiple layers in a 3D chip promises density and performance enhancement. It requires extensive thermal analysis as the power density and temperature
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