Abstract
This paper presents a hardware technique to reduce the static and dynamic power consumption in Functional Units of a 64-bit superscalar processor. Our approach is based on substituting some of the 64-bit power-hungry adders by others with 32-bit lower powerconsumption adders, and modifying the protocol in order to issue as much instructions as possible to those low power-consumption units incurring a negligible performance penalty. Our technique saves between 14.7% and a 50 % of the power-consumption in the adders which is between 6.1% and a 20% of powerconsumption in the execution units. This reduction is important because it can avoid the creation of a hot spot on the functional units.
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