A power-aware design of a Spacer Detector for ternary logic asynchronous digital systems using conventional CMOS process technology

Abstract

Recently, a C-ternary logic asynchronous digital system design was proposed. The advantage of this design was the use of conventional CMOS process technology, which reduced the process cost, instead of the multi-threshold one. However, the design had to use the element called “Spacer Detector”, or “SD”, to detect the half logic. This element design, like an inverter, had the cons that the current is drawn when the half logic is available on the input terminal. This paper proposes a power-aware design of the spacer detector for ternary logic asynchronous digital systems in transistor level. This design still gain the advantage of cost reduction from using conventional CMOS process technology. The SPICE simulation results, based on 0.5μm C5 process, show that this design consumes less power than the previous design for about 25%.