Abstract
With the recent advances of the VLSI technologies, stabilizing the physical behavior of VLSI chips is becoming a very complicated problem. Power grid optimization is required to minimize the risks of timing error by IR drop, defects by electro migration (EM), and manufacturing cost by the chip size. This problem includes complicated tradeoff relationships. We propose a new approach by observing the direct objectives of manufacturing cost, and timing error risk caused by IR drop and EM. The manufacturing cost is based on yield for LSI chip. The optimization is executed in early phase of the physical design, and the purpose is to find the rough budget of decoupling capacitors that may cause block size increase. Rough budgeting of the power wire width is also determined simultaneously. The experimental result shows that our approach enables selection of a cost sensitive result or a performance sensitive result in early physical design phase.
Highlights
With the advent of super deep submicron technologies, designing stable and dependable physical behavior of LSIs is becoming very difficult and serious problems, due to the IR-drop and the electro migration (EM)
We propose a new approach by observing the direct objectives of manufacturing cost, and timing error risk caused by IR drop and EM
IR-drop, EM, wiring and manufacturing cost have been all optimized in this experimentation
Summary
With the advent of super deep submicron technologies, designing stable and dependable physical behavior of LSIs is becoming very difficult and serious problems, due to the IR-drop and the EM. In this paper we propose a new efficient and effective power optimization algorithm, appropriate for current large scale chips It deals directly with the manufacturing cost, which is calculated by the chip area increase caused by inserting the decoupling capacitors. The manufacturing cost information is more effectively optimized in the early physical design phase called floor planning because there is more freedom of shape and size selection of the functional blocks. The risk function is defined for each objective, the wiring congestion, the EM, the timing error due to IR drop, and the chip cost. Most of these are already proposed in other papers [6,7].
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