A power efficient channel selection filter/coarse AGC with no range switching transients

Abstract

This paper presents a channel selection filter/coarse AGC system implemented in a 0.25 /spl mu/m digital CMOS process. The system uses multiple filtering paths, each optimized for part of the required total dynamic range, resulting in small power dissipation (9 mA at 2.5 V) and chip area (0.7 mm/sup 2/). The individual filtering paths operate continuously, providing undisturbed output over the entire time, contrary to conventional AGC-filter schemes. The fabricated prototype maintains a signal/(noise + IM3 distortion) ratio of at least 33 dB, over a 48 dB signal range, with good blocker immunity.