A power constrained simultaneous noise and input matched low noise amplifier design technique

Abstract

In this paper, very simple and insightful sets of noise parameters expressions for a power-constrained simultaneous noise and input matching (PCSNIM) CMOS LNA design technique are newly introduced. Based on the noise parameters expression, the design principle, advantages, and limitations are clearly explained. The proposed LNA is optimized for low voltage, low power 900 MHz Zigbee applications based on 0.25 /spl mu/m CMOS technology. Measurement results show a power gain of 12 dB, NF and NF/sub min/ of 1.35 dB, and IIP3 of -4 dBm while dissipating the DC current of 1.6 mA (only 0.7 mA for NMOS transistor) at a supply voltage of 1.25 V.