A Pollution Alleviative L2 Cache Replacement Policy for Chip Multiprocessor Architecture

Abstract

Chip multi-processor exploits both instruction-level and thread-level parallelism effectively. In a typical chip multi-processor architecture, L2 cache is shared by multiple cores. Sharing the L2 cache allows high cache utilization and avoids duplicating cache hardware resources. Unfortunately, the mis-predictions of any processor core could lead the load miss from the wrong path to write some useless data into the shared L2 cache, and cause L2 cache pollution. This may increase additional cache misses and lessen performance of other threads for failing to occupy sufficient L2 cache space, and even cause threads starvation. This paper proposes a light pollution replacement policy for shared L2 cache, called LPR, which priorities swapping of wrong path data to eliminate the pollution caused by the execution of the wrong path load instructions as soon as possible. Under the configuration of dual-core CMP architecture, 32KB private data/instruction L1 cache, 512KB shared L2 cache, simulation results show that LPR improves the IPC from 1.83% to 7.57% averagely, 11.1% mostly, and increases the L2 cache hit rate from 0.47% to 0.85% averagely, 1.91% mostly, due to the pollution alleviation of the shared L2 cache.