Abstract
This paper represents the design and implementation of a low power 4-bit LFSR using Dual edge triggered flip flop. A linear feedback shift register (LFSR) is assembled by N number of flip flops connected in series and a combinational logic generally xor gate. An LFSR can generate random number sequence which acts as cipher in cryptography. A known text encrypted over long PN sequence, in order to improve security sequence made longer ie 128 bit; require long chain of flip flop leads to more power consumption. In this paper a novel circuit of random sequence generator using dual edge triggered flip flop has been proposed. Data has been generated on every edge of flip flop instead of single edge. A DETFF-LFSR can generate random number require with less number of clock cycle, it minimizes the number of flip flop result in power saving. In this paper we concentrates on the designing of power competent Test Pattern Generator (TPG) using four dual edge triggered flip-flops as the basic building block, overall there is reduction of power around 25% by using these techniques.
Highlights
Random numbers is essential to cryptography, cryptographic protocol AES, RSA, DES etc is depends on random number for encryption
Pseudo number generator built from Linear Feedback Shift Register (LFSR) with judicious selection of the XOR taps feedback path
LFSR can be implemented in the hardware and it makes useful in applications that may require fast generation of a pseudo random sequence[12] LFSR is preferred for test pattern generator and error correction due to its simple hardware structure
Summary
Random numbers is essential to cryptography, cryptographic protocol AES, RSA, DES etc is depends on random number for encryption. For example 128 bit LFSR requires to implement 32 PRNG with 96 bit are hidden protection comes from hidden number. The clock signal controls flip-flops to sample and store their input data on active edge. Dual edge triggered flip-flop (DETFF) can access data on both edges of the clock; it. Fig (a) present a DETFF captures the input data at both positive and negative active edges of the input clock signal. From waveform it seems that Q switches and each edge of clock and data transmission happens on both edges. An L bit LFSR generates the maximal length up to 2^L-1 combinations, figure
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