A PLL with loop bandwidth enhancement for low-noise and fast-settling clock recovery

Abstract

A new adaptation scheme for low noise and fast settling 50 MHz analog phase-locked loop (PLL) is presented. According to the locking status, an extended loop bandwidth enhancement is achieved by the adaptive contol on the charge pump current. First of all, when the phase error is large, such as in the locking mode, the PLL increases the loop bandwidth and achieves fast locking. On the other hand, when the phase error is small, this PLL decreases the loop bandwidth and minimizes output jitters. The relationships of performance aspects to design variables are presented and the basic tradeoffs of the new concept are discussed. A circuit implementation of the adaptive PLL is described in detail and simulation result of a 50 MHz PLL in a 0:15 mum CMOS technology is presented.