A PLL Based FSK Demodulator With Auxiliary Path

Abstract

In this paper, a phase lock loop (PLL) based frequency shift keying (FSK) demodulator with an auxiliary path to achieve the best signal to noise ratio (SNR) and the least added duty cycle distortion to the recovered data is presented. It has been designed to demodulate an FSK signal of 23.2±0.5MHz with bitrate of 300KHz. An auxiliary path which uses phase frequency detector (PFD) of the main PLL with a fully differential charge pump and a differential input slicer demodulates the modulated FSK signal. The auxiliary path keeps the main PLL core undisturbed to avoid injecting extra noise that causes worse bit error rate (BER). The measured recovered data shows a BER of 10−7, better than the required 10−6. The implemented demodulator has an area of 0.07mm2 and drains 125uA of current from a 1.8V supply. It demodulates the incoming signal which passed through a band-pass filter that suppressed the unwanted out-of-band noises. It is integrated in an FSK transceiver of a USB power delivery (PD) chip in 0.14um CMOS technology.