Abstract
Architecture and realization of a 10 Gb/s clock and data recovering demultiplexer (CDR-DMUX) test chip fabricated in a 0.7-/spl mu/m single poly, 16-GHz BiCMOS process are described. The first stage of the circuit is a combination of a 1:2 DMUX and a parallel early-late phase detector, both supplied with 5-GHz clocks from an external VCO. The plastic package does not measurably degrade the differential data input reflection. The 2.3/spl times/2.3 mm/sup 2/ chip dissipates 450 mW at -3.6 V.
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