Abstract
In this paper, we propose the use of silicon carbide (SiC) material in a planar junctionless FET (JLFET) architecture for high-voltage operations. Using calibrated device simulations, we show that the planar SiC JLFET exhibits: 1) a breakdown voltage of ~60 V; 2) a subthreshold slope of 61 mV/decade; and 3) suppressed lateral band-to-band tunneling. In addition, the proposed device exhibits reduced impact of interface traps than the conventional SiC MOSFETs due to the bulk conduction and may not require additional fabrication steps such as counter-doping and annealing to neutralize the semiconductor-oxide traps. The device also gives excellent off-state characteristics and shows promising results as a future device for power MOS devices, system-on-panel, and 3-D-stacked applications.
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