A pixel readout chip in 40 nm CMOS process for high count rate imaging systems with minimization of charge sharing effects

Abstract

We present a prototype chip built in a 40 nm CMOS process for readout of a pixel detector. The prototype chip has a matrix of 18×24 pixels with a pixel pitch of 100 μm. It can operate in both: the single photon counting (SPC) mode and the C8P1 mode. In the SPC mode using the high gain setting the measured ENC is 84 e <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-</sup> rms (for the peaking time of 48 ns), the gain is 79.7 μV/e <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-</sup> , while the effective offset spread is 24 e <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-</sup> rms. In the C8P1 mode, the chip reconstructs full charge deposited in the detector, despite the charge sharing, and it points to a pixel with the largest charge deposition. The chip architecture and preliminary measurements are reported.