Abstract
A new pipelined time-division multiplexing optical bus for implementing a linear array parallel computer architecture is proposed. In this bus system, switches are introduced on the receiving segment of the bus to control the signal delays on the optical waveguide. The states of switches are dynamically programmable under the control of processors according to computation needs. The linear processor arrays based on such buses can be used as building blocks to construct parallel architectures of higher dimensions to achieve improved scalability and performance.
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